The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2003
Filed:
Jun. 05, 2000
Applicant:
Inventor:
Peter Bruce Gillingham, Kanata, CA;
Assignee:
Advanced Memory International, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/200 ;
U.S. Cl.
CPC ...
G06F 1/200 ;
Abstract
A method and apparatus for optimizing the efficiency of a data bus for a memory device. Extra latency is added between the time a memory controller issues a write instruction and the time the data is transferred on the data bus. This additional latency is optimized to reduce the number of idle time slots on the data bus when switching between a read instruction and a write instruction. Programmable registers are provided for adjusting the amount of latency.
Gillingham, Peter. (2003). Read/write timing for maximum utilization of bi-directional read/write bus (U.S. Patent No. 6546476). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6546476
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile