Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller

Abstract

A node controller ( ) includes a processor interface unit ( ), a crossbar unit ( ), and a memory directory interface unit ( ). Request and reply messages pass from the processor interface unit ( ) to the crossbar unit ( ) through a processor interface output queue ( ). The processor interface unit ( ) writes a request message into the processor interface output queue ( ) using a processor interface clock to latch a write address from a write address latch ( ) in a synchronizer ( ). The write address is encoded by a Gray code counter ( ) and latched by a first sync latch ( ) and a second sync latch ( ) using a core clock of the crossbar unit ( ). The output of the second sync latch ( ) provides one of the inputs to a read address latch ( ) using the core clock of the crossbar unit ( ). The read address is provided to the processor interface output queue ( ) so that the request message is presented to the crossbar unit ( ) in its clock domain regardless of the clock frequency of the processor interface unit ( ).