Non-volatile memory with a serial transistor structure with isolated well and method of operation

Abstract

A first plurality of memory cells ( ) connected in series lies within a first well ( ) that is separated and electrically isolated ( ) from a second plurality of memory cells ( et al.) connected in series lying within a second well ( ). In one embodiment, the first and second wells ( ) are doped p-type and are contained within an n-well ( ) and a substrate ( ). Applying a negative voltage to its corresponding bit line and a positive voltage to its corresponding word line programs a predetermined memory cell within the first plurality. A lesser positive voltage than that applied to the predetermined memory cell's word line is applied to all other bit lines and word lines of non-selected memory cells. By utilizing a negative voltage while programming a memory cell, the magnitude of programming voltages is reduced, thereby, removing the need for an elaborate charge pump to generate a much higher programming voltage.