The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2003

Filed:

Mar. 08, 2001
Applicant:
Inventors:

Radoslav Ratchkov, San Jose, CA (US);

Anand Sethuraman, San Jose, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A software tool and method for routing paths in a routing space. A grid is effectively built “on the fly”, therefore reducing the number of grid points which must be plotted. The boundaries of the routing space are defined. Blocks are then defined in the routing space. After the blocks have been defined, grid points are plotted corresponding to the corners of the blocks. The source points and target points are plotted, and grid points are plotted corresponding to the source and target points. Then, the paths from the source points to the target points are plotted along grid points which have been defined in the routing space. This process of defining the grid points not only reduces the size of data needed to describe the available routing space, but preferably obviates the need to run design rule checks.


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