The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2003

Filed:

Jul. 19, 1993
Applicant:
Inventor:

Takashi Hosaka, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

In a method for forming a self-aligned contact in a MOS-type semiconductor device, a gate electrode film is deposited on a semiconductor substrate and an insulating film is deposited on the gate electrode film. The gate electrode film and the insulating film are then patterned such that the portion of the device where the two films are located is higher than any other regions of the device. A side wall insulating film is formed on the side wall of the gate electrode and the insulating film. Source and drain regions are formed in the face of the substrate using the patterned gate electrode film as a mask. A conductor film is then deposited on the exposed surface of the semiconductor substrate, the first insulating film and the side wall insulating film. A flattening film is then deposited to flatten the surface of the semiconductor, and a region of the flattened film and the conductor film which is above the gate electrode film is etched, using a photoresist film as a mask. As a result, the thickness of the photoresist film used as a mask in etching the conductor film is thinnest at the portion above which are located the insulating film and the gate electrode. Consequently, an open space in the photoresist film can be made smaller than the width of the gate electrode, so as to prevent accidental etching of the source and drain regions.


Find Patent Forward Citations

Hosaka, Takashi. (2003). Method of fabricating semiconductor device (U.S. Patent No. 6544852). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6544852

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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