The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2003

Filed:

Jul. 26, 2001
Applicant:
Inventors:

Chun-Lin Chen, Taoyuan, TW;

Ting-S. Wang, Hsinchu Hsien, TW;

Juinn-Sheng Chen, Tainan Hsien, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/968 ;
U.S. Cl.
CPC ...
H01L 2/968 ;
Abstract

The present invention discloses a method for fabricating a non-volatile memory structure from a single layer of polysilicon in a semiconductor substrate, wherein the semiconductor substrate with two active areas, first and second, are divided by isolation regions. In accordance with this method, a doped buried layer is formed in the first active area. Then, a first floating gate is formed on the buried layer and a second floating gate is formed on the second active area from the single layer of polysilicon. Next, two doped regions are formed at opposite sides of the second floating gate in the second active areas. Finally, a floating gate connection line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential.


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