The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2003
Filed:
Mar. 26, 2001
Applicant:
Inventors:
Itaru Yamazaki, Minato-ku, JP;
Nobuyuki Ikumi, Minato-ku, JP;
Assignee:
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
In a circuit design method, an arrangement/wiring section ( ) determines an arrangement and wiring of logical blocks ( ) so that delay limitation information about input signals supplied to the logical blocks ( ) and limitation conditions about a difference of delay times among a pre-charge control signal (ck , ck , ck ) supplied to the corresponding logical lock ( ) and the input signals are satisfied.
Yamazaki, Itaru. (2003). Circuit design apparatus, circuit design method, circuit design program and semiconductor integrated circuit fabrication method (U.S. Patent No. 6543033). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6543033
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile