The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2003
Filed:
Mar. 22, 1999
John G McBride, Ft Collins, CO (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
The present invention is generally directed to a system and method for identifying nodes in a circuit design that are susceptible to floating. In accordance with one aspect of the invention, a method identifies nodes susceptible to floating by first detecting a node that is an output of a pass gate. The method then evaluates the circuit structure surrounding the node to ensure that the surrounding circuit structure is not one of several permissible structures. In this regard, the method ensures that the node is not an output node of a static gate. It also determines that the node is not an output of a multiplexer. If further verifies that the node is not an output of a pass gate that is always on. In addition, the method determines that the node drives a FET gate. In accordance with another aspect a computer readable storage medium, containing program code for evaluating a netlist, may be provided to detect a node that is susceptible to floating comprising. In this regard, the computer readable medium includes a first code segment configured to detect a node that is an output of a pass gate. It further includes a second code segment configured to ensure that the node is not an output node of a static gate. In addition, the computer readable medium includes a third code segment configured to determine that the node is not an output of a multiplexer. It further includes a fourth code segment configured to verify that the node is not an output of a pass gate that is always on. Finally, the computer readable medium includes a fifth code segment configured to determine that the node drives a FET gate.