The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2003

Filed:

May. 10, 1999
Applicant:
Inventor:

Timothy A. Pontius, Lake in the Hills, IL (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/500 ;
U.S. Cl.
CPC ...
G06F 1/500 ;
Abstract

A method of selecting a cache design for a computer system begins with the making of a prototype module with a processor, a “seed” cache, and a trace detection module. The prototype module can be inserted within a system that includes main memory and peripherals. While an application program is run on the system, the communications between the processor and the seed cache are detected and compressed. The compressed detections are stored in a trace capture module and collectively define a trace of the program on the prototype module. The trace is then expanded and used to evaluate a candidate cache design. The expansion and evaluation can be iterated to evaluate many cache designs. The method can be used to pick the cache design with the best performance or as a foundation for performing a cost/performance comparison of the evaluated caches. In this method, a single prototype is used to generate an accurate trace that permits many alternative cache designs to be evaluated. This contrasts with methods that use cacheless models to develop less accurate traces and methods that allow only one cache design to be evaluated per prototype. In summary, the invention provides an accurate and efficient method of evaluating alternative cache designs.


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