The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2003
Filed:
Nov. 24, 1999
Applicant:
Inventor:
Charutosh Dixit, Sunnyvale, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 2/700 ;
U.S. Cl.
CPC ...
G01R 2/700 ;
Abstract
Methods for calculating a total capacitance of a metal wire in an integrated circuit is disclosed. In the present invention, a library containing predetermined wiring topologies is created. Each of the wiring topologies has an associated capacitive value. After extracting a layout topology of a segment of the metal wire, the layout topology is used to find and extract one of the predetermined wiring topologies in the library that corresponds to the layout topology. The associated capacitive value for the extracted wiring topology is used to calculate the total capacitance of the metal wire.