Cell data protection circuit in semiconductor memory device and method of driving refresh mode

Abstract

Disclosed is a cell data protection circuit in a semiconductor memory device and a method of driving a refresh mode in the same. The method includes the steps of disabling a word line in a refresh mode faster than in a normal mode, and initiating a bit line equalizing using a same way of the normal mode, wherein the bit line equalizing is initiated after the word line is completely closed so as to prevent an influence of the bit line equalizing on cell data. The circuit includes a first delay element producing word line disabling and bit line equalizing signals, a second delay part, a third delay part, and a selection part outputting the signals generated from the first delay element on a refresh operation, the selection part outputting the signals generated from the second delay element in a normal operation, wherein the word line disabling signal and bit line equalizing signal are produced so as to satisfy a RAS precharge time (tRP) and a RAS read time (tRWL) after a write command in the normal operation and wherein the word line disabling signal and bit line equalizing signal are produced so as to leave a time interval between the word line disabling signal and bit line equalizing signal.