Nonvolatile semiconductor memory device capable of reducing pre-erase write time and erase method therefor

Abstract

None of memory cells employed in a memory cell array is not put into an overerased state even if erase pulse application for 300 ms is executed four times in a fast cell out of the memory cells. Accordingly, one block in the memory cell array is divided into four regions, and the pre-erase written state of each region is written into an erase frequency storage memory that has memory cells of 3-bit for storing an erase frequency. Then, by referring to the contents of the erase frequency storage memory , pre-erase write and write verify are executed in one region only once every four erase operations. Thus, the region of the pre-erase write executed during one erase operation is made to be one-fourth of the conventional region, shortening a pre-erase write pulse applying time and a write verify time and reducing an increase in the pre-erase write time ascribed to a reduction in operating voltage.