The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2003
Filed:
Dec. 23, 1998
Akira Yumoto, Kanagawa, JP;
Osamu Akimoto, Tokyo, JP;
Sony Corporation, Tokyo, JP;
Abstract
A voltage generating circuit which enables realization of iminiaturization, reduction in operating voltage and reduction in dissipation power, a spatial light modulating element and a display system using the same, and a driving method for display system are disclosed. A pMOS transistor as first level setting means is controlled by a pre-charge signal and an output node is pre-charged to a first level. An nMOS transistor forming a control circuit is controlled in accordance with signals on a scanning line and a data line. A signal for controlling an nMOS transistor as second level setting means is generated to control the ON/OFF state of this transistor. Thus, electric charges are discharged from a capacitor and the output node is set at a second level. The capacitor holds the level of the output node and supplies the level to an electrode as a load. Therefore, a voltage generating circuit which enables simplification of the circuit structure, operation at a low voltage and reduction in dissipation power can be realized.