The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2003

Filed:

Mar. 28, 2001
Applicant:
Inventors:

Steffen Bielski, Garching/Alz, DE;

Kurt Feichtinger, Palling, DE;

Alfons Spies, Seebruck, DE;

Erich Strasser, Trostberg, DE;

Johann Mitterreiter, Chieming, DE;

Hermann Meyer, Weissbach, DE;

Andreas Schroter, Traunstein, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 1/22 ;
U.S. Cl.
CPC ...
H03M 1/22 ;
Abstract

A multi-turn rotary encoder that includes a first code carrier connected with an input shaft, a scanning device that scans the first code carrier and generates an absolute position of the input shaft within one revolution, and a digital code word is present at an output of the scanning device and a second code carrier for measuring the number of revolutions of the input shaft. A reduction gear is arranged between and coupled to the first and second code carriers. The second code carrier includes a magnetic body with at least one north and south pole and a substrate with a spatial arrangement of sensor elements integrated therein, which are sensitive to magnetic fields, is associated with the magnetic body. An evaluation circuit integrated into the substrate, wherein scanning signals, which are phase-shifted with respect to each other, from the sensor elements are supplied, and that the evaluation circuit combines the scanning signals in such a way that a second digital code word is present serially or in parallel at an output of the evaluation circuit. A combination logical device, which is supplied with the first and second digital code words and which forms a resultant multi-digit code word therefrom.


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