The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2003
Filed:
Nov. 28, 2001
Kyoohyun Lim, San Jose, CA (US);
Beomsup Kim, Cupertino, CA (US);
Berkäna Wireless, Inc., San Jose, CA (US);
Abstract
A new linearized transconductance circuit for converting an input into an output has been achieved. This linearized transconductance circuit is especially suited for application in a mixing circuit using a double-balanced cell. The circuit allows optimization of linearity and noise figure without excessive current. The input comprises first and second phases having a differential voltage therebetween. The output comprises first and second phases having a differential current therebetween that is proportional to the differential voltage. The circuit comprises, firstly, first, second, third, and fourth MOS transistors, with each transistor having a gate, a drain, and a source. The gates of the first and third MOS transistors are coupled to the input first phase. The drains of the first and third transistors are coupled to the output first phase. The gates of the second and fourth MOS transistors are coupled to the input second phase. The drains of the second and fourth MOS transistors are coupled to the output second phase. A first constant current source is coupled to the sources of the first and fourth MOS transistors. Finally, a second constant current source is coupled to the sources of second and third MOS transistors.