The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2003

Filed:

Mar. 28, 2001
Applicant:
Inventors:

Jian Zhou, Plano, TX (US);

Robert Payne, Plano, TX (US);

Huanzhang Huang, Dallas, TX (US);

Douglas Wente, Plano, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/017 ; H03K 5/04 ; H03K 7/08 ;
U.S. Cl.
CPC ...
H03K 3/017 ; H03K 5/04 ; H03K 7/08 ;
Abstract

A method and apparatus for correcting the duty cycle of an uncorrected differential clock signal having a sinusoidal characteristic and outputting a corrected differential square wave clock signal. In the method, the uncorrected differential clock signal is provided as an uncorrected differential current to a pair of summing nodes. A correction differential voltage is generated as a signal corresponding to the inverse of the corrected differential clock signal and having a common mode voltage of one of the correction differential signals relative to a common mode voltage of the other of the correction differential voltages that depends on the duty cycle of the uncorrected differential clock signal. A correction differential current is generated, corresponding to the correction differential voltage. The correction differential current is provided to the pair of summing nodes to produce a corrected differential current as the sum of the uncorrected differential current and the correction differential current so as to control the timing of the crossover of the corrected differential current at the pair of summing nodes to provide duty cycle correction. Finally, the corrected differential square wave clock signal is provided by generating a differential square wave voltage corresponding to the corrected differential current.


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