The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2003

Filed:

Apr. 17, 2001
Applicant:
Inventors:

Rajesh Manapat, San Jose, CA (US);

P. Kannan Srinivasagam, San Jose, CA (US);

Assignee:

Cypress Semiconductor Corp., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/9003 ; H03K 1/716 ;
U.S. Cl.
CPC ...
H03K 1/9003 ; H03K 1/716 ;
Abstract

A termination circuit for use on a conductor of a transmission line. The termination circuit generally comprises a first, second, third and fourth transistor. The first transistor may have (i) a first drain node couplable to the conductor, (ii) a first source node couplable to a first power source presenting a first reference voltage, and (iii) a first gate node. The second transistor may have (i) a second drain node couplable to the conductor, (ii) a second source node couplable to a second power source presenting a second reference voltage, and (iii) a second gate node. The third transistor (i) may have a third source node coupled to the first gate node and (ii) may be configured to bias the first gate node to a first voltage below the first reference voltage. The fourth transistor (i) may have a fourth source node coupled to the second gate node and (ii) may be configured to bias the second gate node to a second voltage above the second reference voltage.


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