On-chip capacitor

Abstract

An on-chip capacitor is provided with a P-type silicon substrate, a bottom N-well region formed on said P-type silicon substrate, mutually adjacent first P-well and first N-well regions formed on said bottom N-well region, a first electrode formed on said first N-well region, and a second electrode formed on said first P-well region, a coupling surface is formed with said first N-well region and said first P-well region and a capacitance is formed between a power source voltage and a grounding voltage formed between said first P-well region and said bottom N-well region. Thus it is not necessary to maintain a device region, to form a capacitance, to form wiring or maintain a wiring region as in a conventional MOS capacitance while it is possible to obtain a required decoupling capacitance.