The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2003

Filed:

Sep. 12, 2000
Applicant:
Inventors:

Atsushi Nakamura, Tokyo, JP;

Kazutoshi Wakabayashi, Tokyo, JP;

Yuichi Maruyama, Kanagawa, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

The system synthesizer of the present invention is provided for synthesizing a system containing from a system description, the system description containing a permanent connection statement describing an access from a first circuit to a memory element in an interface circuit, and a behavioral sequential operation statement describing the operation of a second circuit which contains an access from the second circuit to the memory element in the interface circuit. The system synthesizer comprises: a separator for separating the permanent connection statement from the behavioral sequential operation statement; a determining processing unit for determining whether a variable in the system description is ans interface variable indicating the memory element in the interface circuit; an interface circuit synthesizer for synthesizing the interface circuit from the permanent connection statement separated by the separator; a behavior synthesizer for synthesizing a sequential operation circuit from the behavioral sequential operation statement separated by the separator; a merging processing unit for merging the interface circuit with the sequential operation circuit via the memory element indicated by the interface variable; and a mergence result output device for outputting the system produced by the merging processing unit in a hardware description language.


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