The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2003

Filed:

Jun. 13, 2000
Applicant:
Inventor:

Kensuke Torii, Fujimi-machi, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A method is provided for designing a semiconductor integrated circuit having a logic macro-cell ( ), a circular power source wiring ( ) disposed around the logic macro-cell ( ) in a ring shape and a signal wiring ( ) that traverses the circular power source and is led out from the logic macro-cell to an outside. The circular power source wiring ( ) is formed from a first layer Al wiring having a priority wiring direction extending in a lateral direction and a second layer Al wiring having a priority wiring direction extending in a vertical direction. The method includes: the first step of inputting in a library definitions required for automatic placing and routing; the second step of inputting the library and a net list in an automatic placing and routing apparatus; the third step of determining a placement of the logic macro-cell ( ); the fourth step of determining the circuit power source wiring ( ) according to the priority wiring directions; and the fifth step of determining the signal wiring ( ) according to the priority wiring directions. The first step includes the step of inputting definitions for positions of vias ( and ) that mutually connect the first and second layer Al wirings that form the circuit power source wiring ( ). The third step includes the step of designating an orientation of the logic macro-cell ( ), and the step of determining which one of the first and second layers Al wirings is used to form each of the edges that compose the circular power source wiring ( ) according to the designated orientation and the priority wiring directions.


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