The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2003
Filed:
Mar. 15, 2000
Alexander Goldovsky, Philadelphia, PA (US);
Hosahalli R. Srinivas, Irvine, CA (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
An n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. The computation stages for each of the bit positions include a sum computation stage implemented in logic circuitry. For a subset of the bit positions, the corresponding sum computation logic circuitry computes a sum based at least in part on group-generate, group-transmit and intermediate carry signals. Advantageously, the sum computation logic circuitry is configured to exploit differences in delay associated with generation of the group-generate, group-transmit and intermediate carry signals, so as to reduce the total computational delay of the adder. Additional delay reduction may be achieved by configuring the sum computation stages of the adder in accordance with a left-to-right routing of the group-generate and group-transmit signals, such that a most-significant half of a given set of sum bits are generated in the same prefix trees as a least-significant half of the sum bits.