The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2003
Filed:
Oct. 18, 2001
Allen Carl Merrill, Encinitas, CA (US);
Joseph James Balardeta, Carlsbad, CA (US);
Wei Fu, San Diego, CA (US);
Mehmet Eker, Santee, CA (US);
Applied Micro Circuits Corporation, San Diego, CA (US);
Abstract
Circuitry for a phase locked loop (PLL) includes a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; and a second equalizer having an input coupled to an output of the second frequency doubler and an output which is fed into the PLL. Each frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The combination of the two frequency doublers in series quadruples the reference signal into the PLL, which allows the, PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. Advantageously, controls for the selection of the initial reference signal are provided.