The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2003
Filed:
Oct. 31, 2000
Hemanshu D. Bhatt, Troutdale, OR (US);
Shafqat Ahmed, Beaverton, OR (US);
Robindranath Banerjee, Gresham, OR (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A capping layer of an insulator such as silicon nitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon nitride caps on the metal lines. After the formation of such low k silicon oxide dielectric material between the closely spaced apart metal lines and the over silicon nitride caps thereon, a second layer of silicon nitride is deposited over the layer of low k silicon oxide dielectric material. This second silicon nitride layer acts as a protective layer over portions of the layer of low k silicon oxide dielectric material between the metal lines which may be lower that the top surface of the silicon nitride caps on the metal lines to prevent further etching or dishing of those portions of the layer of low k silicon oxide dielectric material during the planarizing step. The structure is then planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon nitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon nitride caps. Vias are then formed through the standard k silicon oxide dielectric layer and the silicon nitride caps down to the metal lines. Since the vias are not formed through the low k silicon oxide dielectric material, formation of the vias does not contribute to poisoning of the vias. However, the presence of the low k silicon oxide dielectric material between the horizontally closely spaced apart metal lines reduces the horizontal capacitance between such metal lines.