The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2003

Filed:

Sep. 03, 1999
Applicant:
Inventors:

Yukiaki Yogo, Nukata-gun, JP;

Shigemitsu Fukatsu, Okazaki, JP;

Assignee:

Denso Corporation, Kariya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A semiconductor device having an offset-gate structure, which can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time. A semiconductor device has the offset-gate structure in which an offset region, at which a gate portion is not formed, is formed between an end of the gate portion and a drain on a silicon substrate. Surfaces of a source, the drain and a gate electrode of the gate portion are silicides to reduce a transistor resistance. Whereas a surface of the offset region formed between the gate portion and the drain does not include silicide. to prevent a potential of an end portion of the gate portion from being identical to a potential of the drain due to silicide. Therefore, it can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time.


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