The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2003

Filed:

Feb. 09, 2000
Applicant:
Inventors:

Marcus Karlsson, Luleå, SE;

Benny Hedman, Luleå, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/48 ; G06F 9/50 ;
U.S. Cl.
CPC ...
G06F 9/48 ; G06F 9/50 ;
Abstract

A method for reducing interrupt load in a multi-processor system is disclosed, whereby two central processors executing a real-time operating system can communicate with each other using a shared memory. A start pointer and end pointer are implemented preferably in logic. By detecting a difference in the logic values for the two pointers, the receiving CPU will receive interrupts only when new data from the sending CPU has arrived in the shared memory and the shared memory was empty. Consequently, the operating system will not be disturbed with unnecessary interruptions, and the interrupt load will thus be low.


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Karlsson, Marcus. (2003). Method for reducing processor interrupt load (U.S. Patent No. 6535942). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6535942

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