The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2003
Filed:
Oct. 01, 1998
Lazslo Arato, Tinton Falls, NJ (US);
William J. Santulli, Tinton Falls, NJ (US);
Globespanvirata, Inc., Red Bank, NJ (US);
Abstract
A physical interface unit and method are disclosed which are configured to receive a data stream which may use any one of a number of data communications protocols, and to transmit the same data stream using another one of the same number of data communications protocols. The physical interface unit is advantageously designed to operate in conjunction with a processor circuit to translate a data stream from a first data protocol to a second data protocol. The physical interface unit includes a first serial interface, a first asynchronous transfer mode (ATM) interface, and a first parallel interface. The physical interface also includes a second serial interface, a second ATM interface, and a second parallel interface. The first serial, ATM, and parallel interfaces are electrically coupled to a first FIFO circuit which interfaces with the processor circuit. Likewise, the second serial, ATM, and parallel interfaces are electrically coupled to a second FIFO circuit which interfaces with the processor circuit. One of the first serial, ATM, and parallel interfaces and one of the second serial, ATM, and parallel interfaces are enabled by a selection circuit. A bi-directional data stream using a first protocol is received from and transmitted to a first data endpoint by the enabled first interface and provided to the processor circuit for protocol translation. The same data stream is transmitted to and received from a second data endpoint from the processor circuit via the enabled second interface.