The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2003
Filed:
Jun. 21, 2001
Tae Kyun Kim, Kyoungki-do, KR;
Hynix Semiconductor Inc., Kyoungki-do, KR;
Abstract
Disclosed is a MOSFET fabrication method capable of forming an ultra shallow junction while ensuring stability in controlling threshold voltage. The disclosed method relies on the use of a sacrificial gate structure to form LDD regions and the addition of side wall spacers to form source/drain regions, followed by the deposition of an interlayer insulating film. The sacrificial gate structure is then removed to form a groove in the interlayer insulating film that exposes a portion of the silicon substrate. A sacrificial oxide is grown on the exposed silicon substrate and impurity ions are implanted through the oxide to adjust the threshold voltage. The sacrificial oxide is then removed and replaced by a high quality gate insulating film. A metal gate electrode is then formed in the groove above the gate insulating film, thereby forming a MOSFET device having a metal gate.