The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2003
Filed:
Jul. 01, 1999
Masahiko Toyonaga, Hyogo, JP;
Kazuo Tsuzuki, Aichi, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A method for designing a layout of a semiconductor device includes the steps of: a) preparing a first layout corresponding to a first netlist and including a component layout and a number n of, or first to n (where n≧2), interconnection planar layouts to be sequentially stacked on the component layout; b) receiving a second netlist, which is different from the first netlist; c) selecting at least one of the interconnection planar layouts from the first layout, the number of the interconnection planar layouts selected being equal to or smaller than n−1; and d) producing a second layout, corresponding to the second netlist, by changing the physical arrangement of the at least one interconnection planar layout selected, the second layout including the component layout, the at least one interconnection planar layout with the changed arrangement, and the other interconnection planar layouts that have not been selected from the first layout.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile