The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2003

Filed:

Feb. 16, 1999
Applicant:
Inventors:

Alexander Or, Nesher, IL;

Haim Rochberger, Netanya, IL;

Ken Benstead, Shrewsbury, MA (US);

Assignee:

3Com Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 1/228 ; H04L 1/256 ;
U.S. Cl.
CPC ...
H04L 1/228 ; H04L 1/256 ;
Abstract

An apparatus for and method of enabling the debugging and testing of complex multilevel PNNI based ATM networks. The invention has applications in networks wherein one or more nodes implement only the Minimum Function PNNI implementation and wherein these modes must operate correctly in a PNNI hierarchy environment. A plurality of PTSEs representing simulated virtual portions of an ATM network are injected into a node under test. The PTSEs represent hierarchical portions of ATM networks that are difficult or impossible to implement. The virtual portions of the networks may or may not have been able to be created using real physical network elements. The method includes first generating the injection file containing all the PTSEs to be simulated and then injecting this file into the node under test. The injection process includes reading the ASCII file, parsing the contents and constructing the topology database by processing the binary version of the contents using already existing PNNI processing routines in the switch.


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