The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2003

Filed:

Mar. 23, 2001
Applicant:
Inventor:

Yoshimasa Yagishita, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

The semiconductor integrated circuit according to the present invention comprises a plurality of receiving circuits each for receiving a plurality of input signals in synchronization with a timing signal. The input signals supplied to each of the receiving circuits are made equal in propagation delay times from their respective input terminals to the receiving circuit. Since the receiving circuits can receive the input signals of little skew, the timing margin required for the reception is minimized. That is, high speed operation becomes possible. At the same time, because the input signals corresponding to each individual receiving circuit are made equal in propagation delay time, the wiring for transmitting the input signals can be arranged in a minimum area. This can reduce the chip area, with reduction in chip costs.


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