The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2003
Filed:
Dec. 19, 2001
Applicant:
Inventor:
David Y. Wang, San Jose, CA (US);
Assignee:
Neoaxiom Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 ;
U.S. Cl.
CPC ...
H03K 3/037 ;
Abstract
A flip-flop circuit with metastability reduction having two internal flip-flops connected in a parallel configuration relative to an input line with a input data delay connected to the data input of one of the flip-flops. The outputs are combined and since at least one of the flip-flop outputs should be stable, if the output of one of the flip-flop goes into a metastable state, the output of the other flip-flop will stabilize it, thus producing a stable output.
Wang, David. (2003). Flip-flop with metastability reduction (U.S. Patent No. 6531905). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6531905
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile