The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2003
Filed:
Sep. 28, 2000
Steven A. Guccione, Austin, TX (US);
Prasanna Sundararajan, Campbell, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus for tolerating defects in a programmable logic device (PLD). A PLD includes a plurality of configurable logic elements and interconnect resources, wherein one or more of the configurable logic elements and interconnect resources have circuit defects. A design program is executed that is suitable for run-time reconfiguration of the PLD. The design program includes executable code that specifies a circuit design and generates a configuration bitstream that implements the circuit design on the programmable logic device. The design program also includes code that selectively skips the configurable logic elements and interconnect resources that contain the defects. In various embodiments, an individual configurable logic element, an entire row, or an entire column of elements can be skipped responsive to an input parameter.