The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2003

Filed:

Mar. 09, 2000
Applicant:
Inventors:

Brent Cameron Beardsley, Tucson, AZ (US);

Michael Thomas Benhase, Tucson, AZ (US);

Gregg Steven Lucas, Tucson, AZ (US);

Juan Antonio Yanes, Tucson, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/108 ;
U.S. Cl.
CPC ...
G06F 1/108 ;
Abstract

In a PCI bus system, a method and system check for errors in rite data transferred from a PCI data source across a PCI bus to the PCI bus system, the data comprising a plurality of blocks. Redundancy calculation logic receives the write data across the PCI bus, calculates a check value for each block of the data transferred across the PCI bus, and updating any previously calculated check value with the calculated check value at a storage location of a storage memory. Data path logic is coupled to the PCI bus and to the storage memory, and responds to a unique identifier of a redundancy write command sent subsequent to completion of the transfer of the write data across the PCI interface. The data path logic responds to the write command unique identifier, detecting the updated calculated check value at the storage location of the storage memory. Error check logic coupled to the data path logic determines whether the detected updated calculated check value indicates an error, and upon the detected updated calculated check value indicating an error, signals the error.


Find Patent Forward Citations

Beardsley, Brent. (2003). Write data error checking in a pci bus system (U.S. Patent No. 6530043). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6530043

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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