Apparatus for and a method of clock tree synthesis allocation wiring

Abstract

In an apparatus for clock tree synthesis allocation wiring, the wiring is appropriately conducting while minimizing the wiring cost and power consumed in operation. A first file stores therein information of operating frequencies of clock lines. Second file stores therein information of a maximum capacity allowed for a clock buffer for each operating frequency obtained according to restriction of electro-migration. A maximum capacity determining device determines a maximum capacity allowed for an operating frequency according to information of the operating frequency from the input device, information of the operating frequencies stored in the first file, and information of the maximum capacity stored in the second file. A tool for clock tree synthesis allocation wiring conducts wiring by assuming the maximum capacity to be a limiting value of a maximum capacity which can be added to each clock buffer.