Internal clock signal delay circuit and method for delaying internal clock signal in semiconductor device

Abstract

An internal clock delay circuit of a semiconductor device and a method for delaying an internal clock of the semiconductor device. The semiconductor device includes a CAS latency signal generator that generates CAS latency signals comprising a first CAS latency signal, a second CAS latency signal and a third CAS latency signal, and an internal clock delay circuit that receives one of the CAS latency signals and an internal clock signal and delays the internal clock signal by a predetermined time in response to the received CAS latency signal. The internal clock delay circuit includes delay circuits that delay the internal clock signal, and the internal clock signal passes through only one among the delay circuits when the semiconductor device operates in the second CAS latency mode. The method includes: inputting an internal clock signal to an internal clock delay circuit, which includes delayers, of a semiconductor device; and inputting CAS latency signals to the internal clock delay circuit to determine CAS latency modes of the semiconductor device; and outputting the internal clock signal through the delay circuits as an output signal of the internal clock signal delay circuit. The internal clock signal passes through one of the delay circuits in a second CAS latency mode and passes through at least two delay circuits among the delay circuits in either a first CAS latency mode or a third CAS latency mode.