The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2003
Filed:
Aug. 04, 2000
Koen Gerard Maria Verhaege, Gistel, BE;
Leslie Ronald Avery, Flemington, NJ (US);
Sarnoff Corporation, Princeton, NJ (US);
Abstract
A circuit for the protection of an output driver NMOS transistor during EOS/ESD stress includes an output driver NMOS transistor and an output driver PMOS transistor connected in series between a Vss line and a Vdd line with the gates of the output driver transistors being connected together. An I/O pad is connected to the junction of the output driver transistors. A pre-driver NMOS transistor and a pre-driver PMOS transistor are connected in series between the Vss line and the Vdd line with the gates of the out-put driver transistors being connected together with the output of the pre-driver transistors being connected to the gates of the output driver transistors. A gate clamp is connected between the Vss line, the I/O pad the junction between the pre-driver transistors and the gate of the output driver NMOS transistor. An ESD clamp is connected between the I/O pad, the Vss line and the gate clamp. The gate clamp may comprise a trigger circuit and an inverter circuit with the trigger circuit being either a capacitor and a resistor, or a resistor, MOS transistor and a Zener diode. The circuit may include a plurality of stages of pre-driver transistors.