The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2003

Filed:

May. 10, 2001
Applicant:
Inventors:

Richard Alexander Erhart, Chandler, AZ (US);

Thomas W. Ciccone, Tempe, AZ (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/00 ;
U.S. Cl.
CPC ...
H03K 5/00 ;
Abstract

A buffered sample-and-hold circuit includes two sampling capacitors for each analog voltage to be sampled. The two sampling capacitors are initially charged simultaneously to the analog voltage to be sampled. One of such sampling capacitors is thereafter temporarily coupled to the input terminal of a unity gain amplifier to pre-charge such input terminal, and any associated parasitic capacitance, to a voltage very near the actual sampled analog voltage. Following such pre-charge operation, that sampling capacitor is de-coupled from the input terminal of the amplifier; the other sampling capacitor is then coupled to the input terminal of the amplifier for establishing the actual sampled voltage at the input terminal of the amplifier.


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