The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2003

Filed:

Jan. 21, 1997
Applicant:
Inventors:

Daniel Phillip Dailey, West Bloomfield, MI (US);

Robert Edward Belke, Jr., West Bloomfield, MI (US);

Jay DeAvis Baker, Dearborn, MI (US);

Achyuta Achari, Canton, MI (US);

Myron Lemecha, Dearborn, MI (US);

Michael George Todd, South Lyon, MI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 9/09 ;
U.S. Cl.
CPC ...
H01R 9/09 ;
Abstract

Method of manufacturing a multi-layer printed circuit board adapted for reduce interfacial sheer stresses includes a laminate substrate having a top layer forming a first major surface, a middle layer having a predetermined thickness and a bottom layer forming a second major surface opposed to the first major surface. Etch resists are disposed on the first and second surfaces corresponding to reverse images of desired conductor patterns. The first and second surfaces are thereafter etched and the photoresist removed. The laminate substrate is secured via a low modules adhesive layer to a major surface of a base. The middle layer of the laminate substrate is thereafter selectively etched so as to isolate selected portions of the first and second surfaces and to define inner connect regions therebetween having a height equal to the predetermined thickness.


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