The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2003
Filed:
Feb. 10, 2000
Theodoros Mihopoulos, Austin, TX (US);
Prasad V. Alluri, Austin, TX (US);
J. Vernon Cole, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A silicon-on-insulator substrate and its method of formation are disclosed. In another embodiment, a method for forming a high-k gate dielectric is disclosed. The silicon-on-insulator substrate is prepared by forming a lattice matched dielectric layer ( ) over a semiconductor substrate ( ). A thermodynamically stable dielectric layer ( ) is then formed over the lattice matched dielectric layer ( ). A semiconductor layer ( ) is then formed over the thermodynamically stable dielectric layer ( ). Formation of the high-k gate dielectric includes the processing steps used to form the silicon-on-insulator substrate and additionally includes bonding a second semiconductor substrate ( ) to the semiconductor layer ( ). The first semiconductor substrate ( ) is then removed to expose the lattice matched dielectric layer ( ). This results in a silicon substrate that has a layer of high-k dielectric material that can be used as the gate dielectric for integrated circuits formed on the substrate.