Integrated package and methods for making same

Abstract

One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system. When a single integrated circuit chip is to be embedded in a substrate, the invention makes possible the simultaneous manufacture of a plurality of such packaged integrated circuit chips in a single large substrate using standard semiconductor or printed circuit photolithographic and processing techniques and then singulating the large substrate into a plurality of smaller substrates, each containing a single integrated circuit chip. Likewise, when more than one integrated circuit chip is embedded in a substrate, a plurality of such structures can be manufactured in a single large substrate and then singulated into a plurality of smaller substrates, each containing more than one integrated circuit chips.