The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6528335 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 04, 2003

Filed:

Feb. 14, 2001
Applicant:
Inventors:

Marlene Isabel Almonte, Mohegan Lake, NY (US);

Harold John Hovel, Katonah, NY (US);

Richard Leo Kleinhenz, Wappingers Falls, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/166 ;
U.S. Cl.
CPC ...
H01L 2/166 ;
Abstract

An electrical method is described for determining the presence of certain defects in the buried oxide of silicon-on-insulator wafers which cause electrical breakdown at voltages low enough to cause failure during circuit processing. The method consists of carrying out current-voltage measurements on gold/silicon/buried oxide/substrate devices isolated by selective etching and analyzing the current-voltage behavior in terms of short circuit defect densities, low voltage breakdown defects, and excess current leakage defects. An additional method for detecting the low voltage breakdown defects is to monitor light flashes which accompany the breakdown.


Find Patent Forward Citations

Almonte, Marlene. (2003). Electrical method for assessing yield-limiting asperities in silicon-on-insulator wafers (U.S. Patent No. 6528335). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6528335

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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