The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2003
Filed:
Apr. 05, 2000
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
An electrically erasable programmable logic device (EEPLD) cell ( ) is disclosed. A folded floating gate ( ) and folded select gate ( ) can form two parallel read current paths (Isense and Isense ). A first read current path (Isense ) may be formed between a first semiconductor region ( ) and a second semiconductor region ( - ), and may be controlled by a first floating gate portion ( - ) and a first select gate portion ( - ). A second read current path (Isense ) may be formed between the first semiconductor region ( ) and a third semiconductor region ( - ) that is coupled to a second semiconductor region ( - ). A second read current path (Isense ) may be controlled by a second floating gate portion ( - ) and a second select gate portion ( - ).