Nonvolatile semiconductor memory device including correction of erratic memory cell data

Abstract

In the nonvolatile semiconductor memory device, a plurality of threshold voltages are associated with the programming of multi-valued information in one memory cell, data is first written into a memory cell having a threshold voltage which is the lowest or furthest away from the threshold voltage corresponding to the erase level, and data is successively written into memory cells having higher threshold voltages, namely, threshold voltages that are successively closer to the erase level, thereby overcoming threshold voltage fluctuations attributed to word line disturbance. The memory device features memory cells each of which has a control gate and a floating gate and facilitated for storing multi-level data; an array of word and data lines, each intersection of which corresponds to an individual memory cell; data latch circuits each of which is coupled to a data line and stores data to be written; and sense latch circuits each of which is coupled to a data line and stores readout data from memory cells coupled to a selected word line. In the nonvolatile memory, when occurrence of an erratic bit is detected based on data stored in the sense latch circuits and in the data latch circuits, the memory cell associated with that erratic bit is corrected.