System and method of verifying the authenticity of input signals

Abstract

A system verifies the authenticity of input signals used in the operation of an apparatus. The system includes two input registers, a microprocessor, and one circuit network for each input signal. Each circuit network generates twin binary signals in response to its input signal. Specifically, twin logic one signals are generated by a circuit network when its input signal goes active state. Conversely, twin logic zero signals are generated when the input signal goes inactive. Each circuit network conveys the first binary signal to a dedicated location in one input register and the second binary signal, after inversion, to a dedicated, mirror-imaged location in the other input register. Whenever any bit in either or both input registers changes, the microprocessor reads both input registers to ascertain the state of the bits they contain. Specifically, the bits in the first input register are read and conveyed to a first work register, with the bits in the second input register being re-inverted, reordered to match again the bit order of the first input register, and conveyed to a second work register. The microprocessor then compares each bit read from one work register with its corresponding twin bit read from the other work register. As long as each bit and its corresponding twin bit match, the microprocessor allows the apparatus to operate according to the dictates of the input signal(s) received. If any bit and its corresponding twin bit fail to match, the microprocessor can take whatever protective action is deemed appropriate.