The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2003

Filed:

Jan. 10, 2001
Applicant:
Inventor:

Koju Aoki, Kasugai, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/087 ;
U.S. Cl.
CPC ...
H03L 7/087 ;
Abstract

A mode control circuit of a PLL circuit for switching the PLL circuit from a high-speed mode to a normal mode. The PLL circuit compares the phase of a reference signal and the phase of a comparison signal to generate a first pulse signal and a second pulse signal, and generates based on the first and second pulse signals a frequency signal that is locked at a desired frequency. The mode control circuit receives the first and second pulse signals from the PLL circuit, generates a mode switch signal representing the normal mode when a difference between a phase of the first pulse signal and a phase of the second pulse signal is within a predetermined range, and, after the mode is switched from the high-speed mode to the normal mode, generates the mode switch signal such that the normal mode is maintained.


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