The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2003

Filed:

Dec. 26, 2000
Applicant:
Inventors:

Mitsumasa Koyanagi, Natori, JP;

Yasunori Okano, Nakai-machi, JP;

Nobuaki Miyakawa, Ebina, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/302 ;
U.S. Cl.
CPC ...
H01L 2/302 ;
Abstract

A three-dimensional semiconductor integrated circuit apparatus which permits ready electrical connection and is resistant to deformation and easy to fabricate and a manufacturing method therefor are provided. A second semiconductor substrate is stacked over a third semiconductor substrate, and a first semiconductor substrate is stacked over the second semiconductor substrate. A second integrated circuit is formed over the surface layer of the second semiconductor substrate, and the integrated circuit side of the second semiconductor substrate is bonded to the integrated circuit side of the first semiconductor substrate, resulting in the electrical connection of the first integrated circuit formed over the surface layer of the first semiconductor substrate and the second integrated circuit. In the second semiconductor substrate is formed embedded wiring of which one end is electrically connected to the second integrated circuit and the other end is exposed from the back side, and the third integrated circuit formed over the surface layer of the third semiconductor substrate and the second integrated circuit are electrically connected to the embedded wiring.


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