The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2003
Filed:
May. 30, 2001
Applicant:
Inventor:
Tadashi Igarashi, Tokyo, JP;
Assignee:
Oki Electric Industry Co., Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/14763 ;
Abstract
A method of manufacturing a semiconductor device, which is capable of reducing or preventing damage of wirings formed over a semiconductor substrate. The method of manufacturing the semiconductor device includes forming a wiring on the surface of a semiconductor substrate with a predetermined circuit formed thereon, forming a resin layer whose surface is substantially flat on the wiring, and processing the back of the semiconductor substrate after the formation of the resin layer.
Quick Actions:
Igarashi, Tadashi. (2003). Methods of manufacturing semiconductor devices that protect interconnect wirings during processing of back substrate surface (U.S. Patent No. 6524933). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6524933
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile