Method of design verification for integrated circuit system and method for generating interface model for design verification

Abstract

In a design process of an integrated circuit system, an interface model is generated between a behavioral model described at a behavioral level and an RTL model connected to the behavioral model. The interface model includes protocol converter, bit precision converter and signal converter. The protocol converter converts the protocol of the behavioral model, from which the concept of “clock” is absent, into that of the RTL model to time the behavior represented by the behavioral model with clock pulses for the RTL model. The bit precision converter converts the decimal point representations or bit widths of input/output data. And the signal converter converts signal lines or signal values for an input/output signal of the behavioral model. By providing an interface model like this, the overall system can have its design verified.