Integer to floating point conversion using one's complement with subsequent correction to eliminate two's complement in critical path

Abstract

For use in a processor having a floating point execution core, logic circuitry for, and a method of, converting negative numbers from integer notation to floating point notation. In one embodiment, the logic circuitry includes: (1) a one's complementer that receives a number in integer notation and inverts the received number to yield an inverted number, (2) a leading bit counter, coupled to the one's complementer, that counts leading bits in the inverted number to yield leading bit data, (3) a shifter, coupled to the one's complementer and the leading bit counter, that normalizes the inverted number based on the leading bit data to yield a shifted inverted number, (4) an adder, coupled to the shifter, that increments the shifted inverted number to yield a fractional portion of the received number in floating point notation and overflow data, the adder renormalizing the fractional portion based on the overflow data and (5) exponent generating circuitry, coupled to the leading bit counter and the adder, that generates an exponent portion of the received number in floating point notation as a function of the leading bit data and the overflow data.