Non-volatile semiconductor memory devices

Abstract

Embodiments relate to a non-volatile semiconductor memory device in which the interface state between the tunnel insulation layer and the floating gate and the interface state between the tunnel insulation layer and the control gate are lower, the operation characteristics are stable, and the data writing/erasing cycle life is long. A non-volatile semiconductor memory device (memory transistor) may include a non-volatile semiconductor memory device with a split-gate structure having a source , a drain , a gate insulation layer , a floating gate , an intermediate insulation layer that functions as a tunnel insulation layer, and a control gate . The intermediate insulation layer is composed of at least three insulation layers and . The first and the second outermost layers and of the three insulation layers respectively contact the floating gate and the control gate , and are composed of silicon oxide layers that are formed by a thermal oxidation method. A selective oxide insulation layer is formed by a selective oxidation method on the floating gate . A silicon oxide layer is formed by a CVD method between the first and the second outermost layers and